EN segmented addressing architecture
LV segmentētā adresēšanas arhitektūra
RU архитектура с сегментной адресацией
FR architecture à adressage segmenté
Definīcija: A memory-access technique typified by Intel 80x86 processors. Memory is divided into 64-KB segments in this architecture for addressing locations under the 16-bit address scheme; 32-bit schemes can address memory in segments as large as 4 GB.
Microsoft Terminology 2023. Entry from the Microsoft Language Portal.
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